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» Logic Synthesis for Engineering Change
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TCAD
2008
112views more  TCAD 2008»
14 years 9 months ago
Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs
Boolean matching is one of the enabling techniques for technology mapping and logic resynthesis of Field Programmable Gate Array (FPGA). SAT-based Boolean matching (SAT-BM) has bee...
Yu Hu, Victor Shih, Rupak Majumdar, Lei He
TCAD
2008
92views more  TCAD 2008»
14 years 9 months ago
IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level
Abstract--This paper proposes an adaptive watermarking technique by modulating some closed cones in an originally optimized logic network (master design) for technology mapping. Th...
Aijiao Cui, Chip-Hong Chang, Sofiène Tahar
EMSOFT
2001
Springer
15 years 2 months ago
Compiler Optimizations for Adaptive EPIC Processors
Abstract. Advances in VLSI technology have lead to a tremendous increase in the density and number of devices that can be manufactured in a single microchip. One of the interesting...
Krishna V. Palem, Surendranath Talla, Weng-Fai Won...
96
Voted
FPGA
2004
ACM
126views FPGA» more  FPGA 2004»
15 years 3 months ago
A synthesis oriented omniscient manual editor
The cost functions used to evaluate logic synthesis transformations for FPGAs are far removed from the final speed and routability determined after placement, routing and timing a...
Tomasz S. Czajkowski, Jonathan Rose
78
Voted
FSTTCS
2009
Springer
15 years 1 months ago
Synthesis of Finite-state and Definable Winning Strategies
ABSTRACT. Church's Problem asks for the construction of a procedure which, given a logical specification on sequence pairs, realizes for any input sequence I an output sequen...
Alexander Rabinovich