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64
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ISSS
1997
IEEE
102views Hardware» more  ISSS 1997»
15 years 1 months ago
An Efficient Model for DSP Code Generation: Performance, Code Size, Estimated Energy
This paper presents a model for simultaneous instruction selection, compaction, and register allocation. An arc mapping model along with logical propositions is used to create an ...
Catherine H. Gebotys
102
Voted
SEW
2007
IEEE
15 years 3 months ago
A Generative Approach to Building a Framework for Hard Real-Time Applications
The communication and tasking infrastructure of a realtime application makes up a significant portion of any embedded control system. Traditionally, the tasking and communication...
Irfan Hamid, Elie Najm, Jérôme Hugues
BIRTHDAY
1999
Springer
15 years 1 months ago
Compilation and Synthesis for Real-Time Embedded Controllers
Abstract. This article provides an overview over two constructive approaches to provably correct hard real-time code generation where hard real-time code is generated from abstract...
Martin Fränzle, Markus Müller-Olm
84
Voted
FCCM
2006
IEEE
144views VLSI» more  FCCM 2006»
15 years 3 months ago
Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA
In this paper, we investigate a combination of two techniques — instruction coding and instruction re-ordering — for optimizing energy in embedded processor control. We presen...
Robert G. Dimond, Oskar Mencer, Wayne Luk
IEEECIT
2005
IEEE
15 years 3 months ago
iCDMdt: Focused the Model Mapping and Performance Optimization in Embedded System Design
This paper proposes a method of model-driven HW/SW co-design in embedded system design and discusses the key technology of model mapping, automatic generating codes and performanc...
Jing Luan, Xuan Cheng, Junzhong Gu