In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
In this paper we introduce Chisel, a new hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific h...
Jonathan Bachrach, Huy Vo, Brian Richards, Yunsup ...
We formalize and study business process systems that are centered around "business artifacts", or simply "artifacts". This approach focuses on data records, kn...
Alin Deutsch, Richard Hull, Fabio Patrizi, Victor ...
We propose the study of visibly pushdown automata (Vpa) for processing XML documents. Vpas are pushdown automata where the input determines the stack operation, and XML documents ...
We present a new technique, failure-oblivious computing, that enables servers to execute through memory errors without memory corruption. Our safe compiler for C inserts checks th...
Martin C. Rinard, Cristian Cadar, Daniel Dumitran,...