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ISMVL
2007
IEEE
245views Hardware» more  ISMVL 2007»
15 years 6 months ago
Fault Tolerant CMOS Logic Using Ternary Gates
In this paper we present fault tolerant CMOS logic using redundancy and ternary signals. The ternary gates are implemented using recharge logic which can be exploited in binary an...
Yngvar Berg, Renè Jensen, Johannes Goplen L...
114
Voted
FOSSACS
2007
Springer
15 years 6 months ago
Logical Reasoning for Higher-Order Functions with Local State
Abstract. We introduce an extension of Hoare logic for call-by-value higherorder functions with ML-like local reference generation. Local references may be generated dynamically an...
Nobuko Yoshida, Kohei Honda, Martin Berger
JSAI
2007
Springer
15 years 6 months ago
Towards Translation of Legal Sentences into Logical Forms
This paper reports our ongoing research effort to develop a system which translates legal texts into logical forms in which we can check for inconsistency. Our logical formalizati...
Makoto Nakamura, Shunsuke Nobuoka, Akira Shimazu
96
Voted
ISQED
2010
IEEE
128views Hardware» more  ISQED 2010»
15 years 5 months ago
Soft error rate determination for nanoscale sequential logic
We analyze the neutron induced soft error rate (SER) by modeling induced error pulse using two parameters, occurrence frequency and probability density function for the pulse widt...
Fan Wang, Vishwani D. Agrawal
106
Voted
ICLP
1998
Springer
15 years 4 months ago
Efficient Implementation of a Linear Logic Programming Language
A number of logic programming languages based on Linear Logic [3] have been proposed. However, the implementation techniques proposed for these languages have relied heavily on th...
Joshua S. Hodas, K. M. Watkins, Naoyuki Tamura, Ky...