Sciweavers

1010 search results - page 186 / 202
» Logics for Contravariant Simulations
Sort
View
ISLPED
2005
ACM
90views Hardware» more  ISLPED 2005»
15 years 7 months ago
Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices
This paper studies the impact on energy efficiency and thermal behavior of design style and clock-gating style in queue and array structures. These structures are major sources of...
Yingmin Li, Mark Hempstead, Patrick Mauro, David B...
MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
15 years 7 months ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood
ISLPED
2003
ACM
95views Hardware» more  ISLPED 2003»
15 years 7 months ago
Power efficient comparators for long arguments in superscalar processors
Traditional pulldown comparators that are used to implement associativeaddressing logic in superscalar microprocessors dissipate energy on a mismatch in any bit position in the co...
Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad ...
FPGA
2003
ACM
120views FPGA» more  FPGA 2003»
15 years 7 months ago
Architecture evaluation for power-efficient FPGAs
This paper presents a flexible FPGA architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based FPGA architectures. Our work has several contri...
Fei Li, Deming Chen, Lei He, Jason Cong
HIPEAC
2009
Springer
15 years 6 months ago
Revisiting Cache Block Superloading
Abstract. Technological advances and increasingly complex and dynamic application behavior argue for revisiting mechanisms that adapt logical cache block size to application charac...
Matthew A. Watkins, Sally A. McKee, Lambert Schael...