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150
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FPGA
2010
ACM
16 years 1 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
146
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STACS
2010
Springer
15 years 11 months ago
2010
Springer
One-counter processes (OCPs) are pushdown processes which operate only on a unary stack alphabet. We study the computational complexity of model checking computation tree logic (CT...
136
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DAC
2009
ACM
15 years 11 months ago
2009
ACM
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
152
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PLDI
2009
ACM
15 years 11 months ago
2009
ACM
We present the first machine-checked correctness proof for information flow control (IFC) based on program dependence graphs (PDGs). IFC based on slicing and PDGs is flow-sensi...
138
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DATE
2009
IEEE
15 years 11 months ago
2009
IEEE
—Accurate timing analysis is crucial for obtaining the optimal clock frequency, and for other design stages such as power analysis. Most methods for estimating propagation delay ...