2501 search results - page 201 / 501 » Logics with Rank Operators |
120
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GLVLSI
1999
IEEE
15 years 9 months ago
1999
IEEE
This paper describes the designs of a saturating adder, multiplier, single MAC unit, and dual MAC unit with one cycle latencies. The dual MAC unit can perform two saturating MAC o...
163
Voted
IJFCS
2006
15 years 4 months ago
2006
The generalized LR parsing algorithm for context-free grammars is extended for the case of Boolean grammars, which are a generalization of the context-free grammars with logical c...
128
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CORR
2007
Springer
15 years 4 months ago
2007
Springer
We propose two alternatives to Xu’s axiomatization of Chellas’s STIT. The first one simplifies its presentation, and also provides an alternative axiomatization of the delib...
134
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CAV
1999
Springer
15 years 9 months ago
1999
Springer
BDDs and their algorithms implement a decision procedure for Quanti ed Propositional Logic. BDDs are a kind of acyclic automata. Unrestricted automata (recognizing unbounded string...
134
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ICCAD
2001
IEEE
16 years 1 months ago
2001
IEEE
Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation...