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ASAP
2008
IEEE
118views Hardware» more  ASAP 2008»
16 years 14 days ago
Bit matrix multiplication in commodity processors
Registers in processors generally contain words or, with the addition of multimedia extensions, short vectors of subwords of bytes or 16-bit elements. In this paper, we view the c...
Yedidya Hilewitz, Cédric Lauradoux, Ruby B....
LICS
2007
IEEE
16 years 8 days ago
A Robust Class of Context-Sensitive Languages
We define a new class of languages defined by multi-stack automata that forms a robust subclass of context-sensitive languages, with decidable emptiness and closure under boolea...
Salvatore La Torre, Parthasarathy Madhusudan, Genn...
FPGA
2004
ACM
147views FPGA» more  FPGA 2004»
15 years 11 months ago
The SFRA: a corner-turn FPGA architecture
FPGAs normally operate at whatever clock rate is appropriate for the loaded configuration. When FPGAs are used as computational devices in a larger system, however, it is better ...
Nicholas Weaver, John R. Hauser, John Wawrzynek
VLDB
2004
ACM
144views Database» more  VLDB 2004»
15 years 11 months ago
Returning Modified Rows - SELECT Statements with Side Effects
SQL in the IBM® DB2® Universal Database™ for Linux®, UNIX®, and Windows® (DB2 UDB) database management product has been extended to support nested INSERT, UPDATE, and DELET...
Andreas Behm, Serge Rielau, Richard Swagerman
FOAL
2009
ACM
15 years 10 months ago
Graph-based specification and simulation of featherweight Java with around advice
In this paper we specify an operational run-time semantics of Assignment Featherweight Java -- a minimal subset of Java with assignments -- with around advice, using graph transfo...
Tom Staijen, Arend Rensink