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DFT
2002
IEEE
103views VLSI» more  DFT 2002»
15 years 9 months ago
Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies
Concurrent error detection (CED) methods are typically employed to provide an indication of the operational health of synchronous circuits during normal functionality. Existing CE...
Thomas Verdel, Yiorgos Makris
FPL
2009
Springer
152views Hardware» more  FPL 2009»
15 years 9 months ago
Clock gating architectures for FPGA power reduction
Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock si...
Safeen Huda, Muntasir Mallick, Jason H. Anderson
CONTEXT
2001
Springer
15 years 9 months ago
On the Dimensions of Context Dependence: Partiality, Approximation, and Perspective
Abstract. In this paper we propose to re-read the past work on formalizing context as the search for a logic of the relationships between partial, approximate, and perspectival the...
Massimo Benerecetti, Paolo Bouquet, Chiara Ghidini
ICLP
2001
Springer
15 years 9 months ago
An Order-Sorted Resolution with Implicitly Negative Sorts
We usually use natural language vocabulary for sort names in order-sorted logics, and some sort names may contradict other sort names in the sort-hierarchy. These implicit negation...
Ken Kaneiwa, Satoshi Tojo
HASE
1999
IEEE
15 years 9 months ago
Model Checking UML Statechart Diagrams Using JACK
Statechart Diagrams provide a graphical notation for describing dynamic aspects of system behaviour within the Unified Modeling Language (UML). In this paper we present a branchin...
Stefania Gnesi, Diego Latella, Mieke Massink