2501 search results - page 358 / 501 » Logics with Rank Operators |
144
click to vote
ICCAD
1999
IEEE
15 years 9 months ago
1999
IEEE
This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ens...
128
click to vote
ISCA
1998
IEEE
15 years 9 months ago
1998
IEEE
Microprocessors and memory systems su er from a growing gap in performance. We introduce Active Pages, a computation model which addresses this gap by shifting data-intensive comp...
124
click to vote
ISSS
1998
IEEE
15 years 9 months ago
1998
IEEE
With the decreasing feature sizes during VLSI fabrication and the dominance of interconnect delay over that of gates, control logic and wiring no longer have a negligible impact o...
129
click to vote
KBSE
1998
IEEE
15 years 9 months ago
1998
IEEE
In this paper we describe a tools environment which automates the validation and maintenance of a requirements model written in many-sorted first order logic. We focus on: a trans...
135
click to vote
AMAST
1998
Springer
15 years 9 months ago
1998
Springer
Abstract. This paper proposes a tool to support reasoning about (partial) correctness of constraint logic programs. The tool infers a speci cation that approximates the semantics o...