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» Loop Striping: Maximize Parallelism for Nested Loops
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VLSISP
2008
147views more  VLSISP 2008»
14 years 8 months ago
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder
Data access usually leads to more than 50% of the power cost in a modern signal processing system. To realize a low-power design, how to reduce the memory access power is a critica...
Yu-Han Chen, Tung-Chien Chen, Chuan-Yung Tsai, Sun...
EUROPAR
2004
Springer
15 years 3 months ago
Architecture-Independent Meta-optimization by Aggressive Tail Splitting
Several optimization techniques are hindered by uncertainties about the control flow in a program, which can generally not be determined by static methods at compile time. We pres...
Michael Rock, Andreas Koch
IPPS
1999
IEEE
15 years 2 months ago
A Graph Based Framework to Detect Optimal Memory Layouts for Improving Data Locality
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
IEEEPACT
2009
IEEE
15 years 4 months ago
Automatic Tuning of Discrete Fourier Transforms Driven by Analytical Modeling
—Analytical models have been used to estimate optimal values for parameters such as tile sizes in the context of loop nests. However, important algorithms such as fast Fourier tr...
Basilio B. Fraguela, Yevgen Voronenko, Markus P&uu...
ECCV
2010
Springer
14 years 11 months ago
Fast and Exact Primal-Dual Iterations for Variational Problems in Computer Vision
The saddle point framework provides a convenient way to formulate many convex variational problems that occur in computer vision. The framework unifies a broad range of data and re...
Jan Lellmann, Dirk Breitenreicher, Christoph Schn&...