20 search results - page 1 / 4 » Low Power Driven Scheduling and Binding |
52
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GLVLSI
1998
IEEE
15 years 1 months ago
1998
IEEE
ISSS
1995
IEEE
15 years 1 months ago
1995
IEEE
Decisions taken at the earliest steps of the design process may have a significantimpact on the characteristics of the final implementation. This paper illustrates how power con...
ISSS
2000
IEEE
15 years 2 months ago
2000
IEEE
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. T...
105
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CODES
2003
IEEE
15 years 2 months ago
2003
IEEE
In this paper, we describe a new methodology based on game theory for minimizing the average power of a circuit during scheduling in behavioral synthesis. The problem of schedulin...
ISCAS
2006
IEEE
15 years 3 months ago
2006
IEEE
In this paper we present two polynomial time-complexity heuristic algorithms for optimization of gate-oxide leakage (tunneling current) during behavioral synthesis through simulta...