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» Low Power Driven Scheduling and Binding
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CGO
2004
IEEE
13 years 10 months ago
FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths
Application-specific instruction set processors (ASIPs) have the potential to meet the challenging cost, performance, and power goals of future embedded processors by customizing ...
Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv...
DATE
1999
IEEE
73views Hardware» more  DATE 1999»
13 years 10 months ago
Channel-Based Behavioral Test Synthesis for Improved Module Reachability
We introduce a novel behavioral test synthesis methodology that attempts to increase module reachability, driven by powerful global design path analysis. Based on the notion of tr...
Yiorgos Makris, Alex Orailoglu
CASES
2007
ACM
13 years 10 months ago
Application driven embedded system design: a face recognition case study
The key to increasing performance without a commensurate increase in power consumption in modern processors lies in increasing both parallelism and core specialization. Core speci...
Karthik Ramani, Al Davis
DAC
2005
ACM
14 years 7 months ago
User-perceived latency driven voltage scaling for interactive applications
Power has become a critical concern for battery-driven computing systems, on which many applications that are run are interactive. System-level voltage scaling techniques, such as...
Le Yan, Lin Zhong, Niraj K. Jha
ISQED
2006
IEEE
109views Hardware» more  ISQED 2006»
14 years 8 days ago
Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher perm...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...