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IMS
2000
123views Hardware» more  IMS 2000»
15 years 5 months ago
Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler
Many architectural ideas that appear to be useful from a hardware standpoint fail to achieve wide acceptance due to lack of compiler support. In this paper we explore the design of...
David Judd, Katherine A. Yelick, Christoforos E. K...
MOBIHOC
2008
ACM
16 years 1 months ago
Energy efficient multi-path communication for time-critical applications in underwater sensor networks
Due to the long propagation delay and high error rate of acoustic channels, it is very challenging to provide reliable data transfer for time-critical applications in an energy-ef...
Zhong Zhou, Jun-Hong Cui
ISLPED
2005
ACM
100views Hardware» more  ISLPED 2005»
15 years 7 months ago
A tunable bus encoder for off-chip data buses
Off-Chip buses constitute a significant portion of the total system power in embedded systems. Past research has focused on encoding contiguous bit positions in data values to red...
Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Wa...
MSS
1993
IEEE
62views Hardware» more  MSS 1993»
15 years 6 months ago
Striped Tape Arrays
A growing number of applications require high capacity, high throughput tertiary storage systems 1 2 . We are investigating how data striping ideas apply to arrays of magnetic tap...
Ann L. Drapeau, Randy H. Katz
DSD
2007
IEEE
132views Hardware» more  DSD 2007»
15 years 5 months ago
On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology
In this study, we investigate different cache fault tolerance techniques to determine which will be most effective when on-chip memory cell defect probabilities exceed those of cu...
David Roberts, Nam Sung Kim, Trevor N. Mudge