1307 search results - page 181 / 262 » Low Power Hardware for a High Performance PDA |
112
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FCCM
2009
IEEE
15 years 8 months ago
2009
IEEE
The Ambric Massively Parallel Processor Array (MPPA) is a device that contains 336 32-bit RISC processors and is appropriate for embedded systems due to its relatively small physi...
136
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HPCA
2000
IEEE
15 years 6 months ago
2000
IEEE
Efficiency of synchronization mechanisms can limit the parallel performance of many shared-memory applications. In addition, the ever increasing performance gap between processor...
111
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DATE
2008
IEEE
15 years 8 months ago
2008
IEEE
— Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shi...
110
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ICCD
2006
IEEE
15 years 11 months ago
2006
IEEE
This paper presents a new scheduling technique to improve the speed, power, and scalability of a dynamic scheduler. In a high-performance superscalar processor, the instruction sc...
135
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VLSID
2007
IEEE
16 years 2 months ago
2007
IEEE
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...