Sciweavers

1307 search results - page 187 / 262
» Low Power Hardware for a High Performance PDA
Sort
View
ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
15 years 7 months ago
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi,...
ISCA
2006
IEEE
154views Hardware» more  ISCA 2006»
15 years 8 months ago
SODA: A Low-power Architecture For Software Radio
The physical layer of most wireless protocols is traditionally implemented in custom hardware to satisfy the heavy computational requirements while keeping power consumption to a ...
Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scot...
JSA
2008
91views more  JSA 2008»
15 years 1 months ago
Using supplier locality in power-aware interconnects and caches in chip multiprocessors
Conventional snoopy-based chip multiprocessors take an aggressive approach broadcasting snoop requests to all nodes. In addition each node checks all received requests. This appro...
Ehsan Atoofian, Amirali Baniasadi
EUROPAR
2004
Springer
15 years 7 months ago
Feasibility of QoS for SMT
Since embedded systems require ever more compute power, SMT processors are viable candidates for future high performance embedded processors. However, SMTs exhibit unpredictable pe...
Francisco J. Cazorla, Peter M. W. Knijnenburg, Riz...
APCSAC
2005
IEEE
15 years 7 months ago
The Challenges of Massive On-Chip Concurrency
Moore’s law describes the growth in on-chip transistor density, which doubles every 18 to 24 months and looks set to continue for at least a decade and possibly longer. This grow...
Kostas Bousias, Chris R. Jesshope