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JSAC
2007
108views more  JSAC 2007»
15 years 1 months ago
Optimal relay functionality for SNR maximization in memoryless relay networks
We explore the SNR-optimal relay functionality in a memoryless relay network, i.e. a network where, during each channel use, the signal transmitted by a relay depends only on the ...
Krishna Srikanth Gomadam, Syed Ali Jafar
ICCD
2003
IEEE
129views Hardware» more  ICCD 2003»
15 years 11 months ago
Reducing dTLB Energy Through Dynamic Resizing
Translation Look-aside Buffer (TLB), which is small Content Addressable Memory (CAM) structure used to translate virtual addresses to physical addresses, can consume significant ...
Victor Delaluz, Mahmut T. Kandemir, Anand Sivasubr...
ISCA
2009
IEEE
214views Hardware» more  ISCA 2009»
15 years 8 months ago
Phastlane: a rapid transit optical routing network
Tens and eventually hundreds of processing cores are projected to be integrated onto future microprocessors, making the global interconnect a key component to achieving scalable c...
Mark J. Cianchetti, Joseph C. Kerekes, David H. Al...
ISLPED
2009
ACM
100views Hardware» more  ISLPED 2009»
15 years 8 months ago
Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits
Post-fabrication tuning for mitigating manufacturing variability is receiving a significant attention. To reduce leakage increase involved in performance compensation by body bia...
Koichi Hamamoto, Masanori Hashimoto, Yukio Mitsuya...
EGH
2004
Springer
15 years 7 months ago
A flexible simulation framework for graphics architectures
In this paper we describe a multipurpose tool for analysis of the performance characteristics of computer graphics hardware and software. We are developing Qsilver, a highly con...
Jeremy W. Sheaffer, David P. Luebke, Kevin Skadron