1307 search results - page 191 / 262 » Low Power Hardware for a High Performance PDA |
134
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ETT
2007
15 years 1 months ago
2007
A powerful class of rate-compatible serially concatenated convolutional codes (SCCCs) has been proposed based on minimizing analytical upper bounds on the error probability in the ...
115
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ISCA
2008
IEEE
15 years 8 months ago
2008
IEEE
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
127
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SBCCI
2004
ACM
15 years 7 months ago
2004
ACM
Digital Control System in the industry has been used in most of the applications based on expensive Programmable Logical Controllers (PLC). These Systems are, in general, highly c...
140
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IPPS
2008
IEEE
15 years 8 months ago
2008
IEEE
Large scale hardware-supported multithreading, an attractive means of increasing computational power, benefits significantly from low per-thread costs. Hardware support for ligh...
105
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FPGA
2003
ACM
15 years 7 months ago
2003
ACM
This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has bee...