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IPPS
2008
IEEE
15 years 8 months ago
Build to order linear algebra kernels
—The performance bottleneck for many scientific applications is the cost of memory access inside linear algebra kernels. Tuning such kernels for memory efficiency is a complex ...
Jeremy G. Siek, Ian Karlin, Elizabeth R. Jessup
ACCV
2006
Springer
15 years 7 months ago
Boosted Algorithms for Visual Object Detection on Graphics Processing Units
Nowadays, the use of machine learning methods for visual object detection has become widespread. Those methods are robust. They require an important processing power and a high mem...
Hicham Ghorayeb, Bruno Steux, Claude Laurgeau
89
Voted
CGO
2005
IEEE
15 years 7 months ago
SWIFT: Software Implemented Fault Tolerance
To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. Howev...
George A. Reis, Jonathan Chang, Neil Vachharajani,...
125
Voted
DFT
2003
IEEE
142views VLSI» more  DFT 2003»
15 years 7 months ago
Exploiting Instruction Redundancy for Transient Fault Tolerance
This paper presents an approach for integrating fault-tolerance techniques into microprocessors by utilizing instruction redundancy as well as time redundancy. Smaller and smaller...
Toshinori Sato
EMSOFT
2004
Springer
15 years 7 months ago
Remote customization of systems code for embedded devices
Dedicated operating systems for embedded systems are fast being phased out due to their use of manual optimization, which provides high performance and small footprint, but also r...
Sapan Bhatia, Charles Consel, Calton Pu