Sciweavers

1307 search results - page 230 / 262
» Low Power Hardware for a High Performance PDA
Sort
View
ISQED
2007
IEEE
160views Hardware» more  ISQED 2007»
15 years 8 months ago
On-Chip Inductance in X Architecture Enabled Design
The inductance effects become significant for sub-100nm process designs due to increasing interconnect lengths, lower interconnect resistance values and fast signal transition tim...
Santosh Shah, Arani Sinha, Li Song, Narain D. Aror...
124
Voted
ISCA
2005
IEEE
144views Hardware» more  ISCA 2005»
15 years 7 months ago
Scalable Load and Store Processing in Latency Tolerant Processors
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth...
MOBIHOC
2005
ACM
16 years 1 months ago
On the node-scheduling approach to topology control in ad hoc networks
: In this paper, we analyze the node scheduling approach of topology control in the context of reliable packet delivery. In node scheduling, only a minimum set of nodes needed for ...
Budhaditya Deb, Badri Nath
MOBIHOC
2003
ACM
16 years 1 months ago
SHORT: self-healing and optimizing routing techniques for mobile ad hoc networks
On demand routing protocols provide scalable and costeffective solutions for packet routing in mobile wireless ad hoc networks. The paths generated by these protocols may deviate ...
Chao Gui, Prasant Mohapatra
ISCA
2011
IEEE
258views Hardware» more  ISCA 2011»
14 years 5 months ago
A case for heterogeneous on-chip interconnects for CMPs
Network-on-chip (NoC) has become a critical shared resource in the emerging Chip Multiprocessor (CMP) era. Most prior NoC designs have used the same type of router across the enti...
Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. ...