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» Low Power Hardware for a High Performance PDA
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ICS
2005
Tsinghua U.
15 years 7 months ago
Low-power, low-complexity instruction issue using compiler assistance
In an out-of-order issue processor, instructions are dynamically reordered and issued to function units in their dataready order rather than their original program order to achiev...
Madhavi Gopal Valluri, Lizy Kurian John, Kathryn S...
108
Voted
LCTRTS
2010
Springer
15 years 8 months ago
Operation and data mapping for CGRAs with multi-bank memory
Coarse Grain Reconfigurable Architectures (CGRAs) promise high performance at high power efficiency. They fulfil this promise by keeping the hardware extremely simple, and movi...
Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Yunh...
139
Voted
SASP
2009
IEEE
291views Hardware» more  SASP 2009»
15 years 8 months ago
FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs
— As growing power dissipation and thermal effects disrupted the rising clock frequency trend and threatened to annul Moore’s law, the computing industry has switched its route...
Alexandros Papakonstantinou, Karthik Gururaj, John...
IEEEPACT
2005
IEEE
15 years 7 months ago
A Simple Divide-and-Conquer Approach for Neural-Class Branch Prediction
The continual demand for greater performance and growing concerns about the power consumption in highperformance microprocessors make the branch predictor a critical component of ...
Gabriel H. Loh
CNSR
2005
IEEE
15 years 3 months ago
An Integrated Error Control and Constrained Sequence Code Based on Multimode Coding
We present a method of integrating constrained sequence (CS) and error control (EC) codes for digital communication systems. This technique is based on multimode coding where a si...
A. Hughes, I. J. Fair