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DATE
1999
IEEE
129views Hardware» more  DATE 1999»
15 years 4 months ago
Battery-Powered Digital CMOS Design
In this paper, we consider the problem of maximizing the battery life (or duration of service) in battery-powered CMOS circuits. We first show that the battery efficiency (or utili...
Massoud Pedram, Qing Wu
VLSID
2003
IEEE
115views VLSI» more  VLSID 2003»
16 years 3 days ago
An Adaptive Supply-Voltage Scheme for Low Power Self-Timed CMOS Digital Design
This paper combines an adaptive supply-voltage scheme with self-timed CMOS digital design, to achieve low power performance. The supply-voltage automatically tracks the input data...
W. Kuang, J. S. Yuan
IWSOC
2005
IEEE
141views Hardware» more  IWSOC 2005»
15 years 5 months ago
Design and Optimization of Low-Voltage Low-Power Quasi-Floating Gate Digital Circuits
This paper explores the design and optimization of Quasi-Floating Gate MOS techniques to lowvoltage/low-power digital circuitry. The simulated power consumption of standard CMOS g...
Kenneth A. Townsend, James W. Haslett, Krzysztof I...
GLVLSI
2010
IEEE
189views VLSI» more  GLVLSI 2010»
15 years 4 months ago
8Gb/s capacitive low power and high speed 4-PWAM transceiver design
In this paper, capacitive 4-PWAM transmitter architectures and circuits are proposed and its performances are analyzed with random jitter and PVT variation comparing with other wo...
Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi
VLSID
2004
IEEE
128views VLSI» more  VLSID 2004»
16 years 3 days ago
A Compact Low-Power Buffer Amplifier with Dynamic Bias Control Technique
This work presents a novel dynamic bias control technique to verify the circuit performance of the lowpower rail-to-rail input/output buffer amplifier, which can be operating in s...
Chih-Jen Yen, Wen-Yaw Chung, Mely Chen Chi