240 search results - page 16 / 48 » Low energy asynchronous architectures |
101
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VLSID
2010
IEEE
15 years 1 months ago
2010
IEEE
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...
DSD
2002
IEEE
15 years 2 months ago
2002
IEEE
This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum...
95
Voted
DAC
2006
ACM
15 years 10 months ago
2006
ACM
Designing an energy efficient power gating structure is an important and challenging task in Multi-Threshold CMOS (MTCMOS) circuit design. In order to achieve a very low power des...
87
Voted
DAC
2009
ACM
15 years 10 months ago
2009
ACM
In this paper, we propose PDRAM, a novel energy efficient main memory architecture based on phase change random access memory (PRAM) and DRAM. The paper explores the challenges in...
EENERGY
2010
14 years 10 months ago
2010
Energy efficient networks are becoming a hot research topic, and the networking community is increasingly devoting its attention to the identification of approaches to save energy...