67 search results - page 10 / 14 » Low power architecture for high speed packet classification |
SIPS
2008
IEEE
15 years 4 months ago
2008
IEEE
Modern microprocessor technology is migrating from simply increasing clock speeds on a single processor to placing multiple processors on a die to increase throughput and power pe...
NPL
2006
14 years 9 months ago
2006
The authors previously proposed a self-organizing Hierarchical Cerebellar Model Articulation Controller (HCMAC) neural network containing a hierarchical GCMAC neural network and a ...
DAC
1997
ACM
15 years 1 months ago
1997
ACM
An ATPG technique is proposed that reduces heat dissipation during testing of sequential circuits that have full-scan. The objective is to permit safe and inexpensive testing of l...
TVLSI
2008
14 years 9 months ago
2008
Applications in computer networks often require high throughput access to large data structures for lookup and classification. While advanced algorithms exist to speed these search...
APCSAC
2005
IEEE
15 years 3 months ago
2005
IEEE
Moore’s law describes the growth in on-chip transistor density, which doubles every 18 to 24 months and looks set to continue for at least a decade and possibly longer. This grow...