67 search results - page 6 / 14 » Low power architecture for high speed packet classification |
GLVLSI
2007
IEEE
15 years 3 months ago
2007
IEEE
Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3, 2), (7, 3...
MICRO
2003
IEEE
15 years 2 months ago
2003
IEEE
Abstract—High-speed routers often use commodity, fully-associative, TCAMs (Ternary Content Addressable Memories) to perform packet classification and routing (IP lookup). We prop...
ICCAD
1994
IEEE
15 years 1 months ago
1994
IEEE
Application Specific Instruction-Set Processors (ASIPs) offer designers the ability for high-speed data and control processing with the added flexibility needed for late design sp...
OSDI
2008
ACM
15 years 10 months ago
2008
ACM
Active research is being conducted in reducing power consumption of all the components of the Internet. To that end, we propose schemes for power reduction in network switches - T...
GI
2004
Springer
15 years 3 months ago
2004
Springer
Abstract: File-sharing in mobile networks has differing demands to a P2P architecture. Resource access and mediation techniques must follow constraints given in 2.5G/3G networks. E...