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» Low power architecture for high speed packet classification
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INFOCOM
2007
IEEE
15 years 3 months ago
Small Active Counters
— The need for efficient counter architecture has arisen for the following two reasons. Firstly, a number of data streaming algorithms and network management applications requir...
Rade Stanojevic
SIGCOMM
2010
ACM
14 years 9 months ago
c-Through: part-time optics in data centers
Data-intensive applications that operate on large volumes of data have motivated a fresh look at the design of data center networks. The first wave of proposals focused on designi...
Guohui Wang, David G. Andersen, Michael Kaminsky, ...
ISVLSI
2003
IEEE
138views VLSI» more  ISVLSI 2003»
15 years 2 months ago
Bouncing Threads: Merging a New Execution Model into a Nanotechnology Memory
The need for small, high speed, low power computers as the end of Moore’s law approaches is driving research into nanotechnology. These novel devices have significantly differe...
Sarah E. Frost, Arun Rodrigues, Charles A. Giefer,...
DAC
2005
ACM
15 years 10 months ago
Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method
This paper presents a novel repeater insertion algorithm for the power minimization of realistic interconnect trees under given timing budgets. Our algorithm judiciously combines ...
Yuantao Peng, Xun Liu
NCA
2003
IEEE
15 years 2 months ago
Network Assisted IP Mobility Support in Wireless LANs
In recent years, wide bandwidth and low cost wireless LAN (WLAN) technology has emerged as a competitive choice for high speed wireless Internet access. To support the Internet mo...
Wei Wu, Nilanjan Banerjee, Kalyan Basu, Sajal K. D...