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» Low power architecture for high speed packet classification
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HPCA
2009
IEEE
15 years 10 months ago
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
Magnetic Random Access Memory (MRAM) is considered to be a promising future memory technology due to its low leakage power, high density and fast read speed. The heterogeneous int...
Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yira...
GECCO
2007
Springer
207views Optimization» more  GECCO 2007»
15 years 3 months ago
A data parallel approach to genetic programming using programmable graphics hardware
In recent years the computing power of graphics cards has increased significantly. Indeed, the growth in the computing power of these graphics cards is now several orders of magn...
Darren M. Chitty
APCSAC
2006
IEEE
15 years 3 months ago
A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster
In the ubiquitous era, it is necessary to research the architectures of multiprocessor system with high performance and low power consumption. A simulator developed in high level l...
Arata Shinozaki, Masatoshi Shima, Minyi Guo, Mitsu...
CF
2005
ACM
14 years 11 months ago
An efficient wakeup design for energy reduction in high-performance superscalar processors
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
Kuo-Su Hsiao, Chung-Ho Chen
CONEXT
2009
ACM
14 years 10 months ago
BUFFALO: bloom filter forwarding architecture for large organizations
In enterprise and data center networks, the scalability of the data plane becomes increasingly challenging as forwarding tables and link speeds grow. Simply building switches with...
Minlan Yu, Alex Fabrikant, Jennifer Rexford