169 search results - page 10 / 34 » Low power architecture of the soft-output Viterbi algorithm |
89
Voted
CODES
2007
IEEE
15 years 6 months ago
2007
IEEE
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...
HPCC
2007
Springer
15 years 5 months ago
2007
Springer
Abstract. Low-power design became crucial with the widespread use of the embedded systems, where a small battery has to last for a long period. The embedded processors need to efï¬...
103
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LCTRTS
2007
Springer
15 years 5 months ago
2007
Springer
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
98
Voted
ISLPED
2003
ACM
15 years 4 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
93
Voted
IJCSA
2008
14 years 11 months ago
2008
This paper presents a comparison relating two different vision system architectures. The first one involves a smart sensor including analog processors allowing on-chip image proce...