169 search results - page 24 / 34 » Low power architecture of the soft-output Viterbi algorithm |
117
Voted
VLSID
2007
IEEE
16 years 1 days ago
2007
IEEE
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
79
Voted
DAC
2006
ACM
16 years 19 days ago
2006
ACM
Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source...
DAC
2008
ACM
16 years 20 days ago
2008
ACM
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...
105
Voted
CSCW
2006
ACM
15 years 5 months ago
2006
ACM
We evaluate response times, in N-user collaborations, of the popular centralized (client-server) and replicated (peer-to-peer) architectures, and a hybrid architecture in which ea...
124
Voted
DEBS
2010
ACM
15 years 3 months ago
2010
ACM
We present a case study parallelizing streaming aggregation on three different parallel hardware architectures. Aggregation is a performance-critical operation for data summarizat...