169 search results - page 2 / 34 » Low power architecture of the soft-output Viterbi algorithm |
VLSISP
1998
14 years 11 months ago
1998
This paper describes the architecture and the performance of a new programmable 16-bit Digital Signal Processor (DSP) engine. It is developed specifically for next generation wire...
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IWSOC
2005
IEEE
15 years 5 months ago
2005
IEEE
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...
VLSID
1997
IEEE
15 years 3 months ago
1997
IEEE
I n this paper, we first present a pipelined delayed least mean square (DLMS) adaptive filter architecture whose power dissipation meets a specified budget. This low-power archite...
TCOM
2010
14 years 10 months ago
2010
—We propose an improved minimum mean square error (MMSE) vertical Bell Labs layered space-time (V-BLAST) detection technique, called a soft input, soft output, and soft feedback ...
VLSID
2005
IEEE
15 years 12 months ago
2005
IEEE
This paper presents two schemes for the implementation of high performance and low power FIR filtering Intellectual Property (IP) cores. Low power is achieved through the utilizat...