143 search results - page 2 / 29 » Low power data processing by elimination of redundant comput... |
100
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DCC
2005
IEEE
16 years 23 days ago
2005
IEEE
We analyze the technique for reducing the complexity of entropy coding consisting in the a priori grouping of the source alphabet symbols, and in dividing the coding process in tw...
109
Voted
ICCAD
2001
IEEE
15 years 10 months ago
2001
IEEE
Abstract: We propose an effective algorithm for power optimization in behavioral synthesis. In previous work, it has been shown that several hardware allocation/binding problems fo...
132
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WMPI
2004
ACM
15 years 6 months ago
2004
ACM
The size and speed of first-level caches and SRAMs of embedded processors continue to increase in response to demands for higher performance. In power-sensitive devices like PDAs a...
116
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CGO
2005
IEEE
15 years 6 months ago
2005
IEEE
Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-p...
103
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DATE
2006
IEEE
15 years 7 months ago
2006
IEEE
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...