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GLVLSI
2000
IEEE
90views VLSI» more  GLVLSI 2000»
13 years 10 months ago
Low power high speed analog-to-digital converter for wireless communications
A new ADC architecture is devised. This architecture is memory based, in which the last sample is used to predict the current one, resulting in both power dissipation and energy r...
A. E. Hussein, Mohamed I. Elmasry
IEICET
2008
106views more  IEICET 2008»
13 years 5 months ago
Realization of Low Power High-Speed Channel Filters with Stringent Adjacent Channel Attenuation Specifications for Wireless Comm
Finite impulse response (FIR) filtering is the most computationally intensive operation in the channelizer of a wireless communication receiver. Higher order FIR channel filters a...
Jimson Mathew, R. Mahesh, A. Prasad Vinod, Edmund ...
ICCD
2002
IEEE
115views Hardware» more  ICCD 2002»
14 years 2 months ago
Low-Power, High-Speed CMOS VLSI Design
Ubiquitous computing is a next generation information technology where computers and communications will be scaled further, merged together, and materialized in consumer applicati...
Tadahiro Kuroda
GLOBECOM
2010
IEEE
13 years 3 months ago
Analog Equalization for Low Power 60 GHz Receivers in Realistic Multipath Channels
Multi-gigabit per second wireless network devices are emerging for personal area networks (PAN) in the 60 GHz band. Such devices are typically power hungry, largely due to the requ...
Khursheed Hassan, Theodore S. Rappaport, Jeffrey G...
ICRA
1998
IEEE
129views Robotics» more  ICRA 1998»
13 years 10 months ago
Antenna Pointing for High Bandwidth Communications from Mobile Robots
This paper discusses the challenge of achieving high bandwidth, distant range wireless communication from mobile robots by way of antenna tracking. In the case of robots traversin...
Deepak Bapna, Eric Rollins, Alex Foessel, William ...