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» Low power implementation of high throughput FIR filters
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TSP
2008
158views more  TSP 2008»
13 years 6 months ago
High-Speed VLSI Implementation of 2-D Discrete Wavelet Transform
This paper presents a systematic high-speed VLSI implementation of the discrete wavelet transform (DWT) based on hardware-efficient parallel FIR filter structures. High-speed 2-D D...
Chao Cheng, Keshab K. Parhi
FPL
2003
Springer
146views Hardware» more  FPL 2003»
13 years 11 months ago
Domain-Specific Reconfigurable Array for Distributed Arithmetic
Distributed Arithmetic techniques are widely used to implement Sum-of-Products computations such as calculations found in multimedia applications like FIR filtering and Discrete Co...
Sami Khawam, Tughrul Arslan, Fred Westall
APCCAS
2006
IEEE
233views Hardware» more  APCCAS 2006»
14 years 15 days ago
Jointly Optimized Modulated-Transmitter and Receiver FIR MIMO Filters
— In recent years, several approaches have been proposed aiming the optimal joint design of finite impulse response (FIR) multiple-input multiple-output (MIMO) transmitter and r...
Guilherme Pinto, Paulo S. R. Diniz, Are Hjø...
ISLPED
2000
ACM
107views Hardware» more  ISLPED 2000»
13 years 10 months ago
Low power mixed analog-digital signal processing
The power consumption of mixed-signal systems featured by an analog front-end, a digital back-end, and with signal processing tasks that can be computed with multiplications and a...
Mattias Duppils, Christer Svensson
ICES
2010
Springer
277views Hardware» more  ICES 2010»
13 years 4 months ago
An Efficient, High-Throughput Adaptive NoC Router for Large Scale Spiking Neural Network Hardware Implementations
Recently, a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an ef...
Snaider Carrillo, Jim Harkin, Liam McDaid, Sandeep...