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» Low threshold CMOS circuits with low standby current
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88
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GLVLSI
2006
IEEE
145views VLSI» more  GLVLSI 2006»
15 years 5 months ago
Leakage current starved domino logic
A new circuit technique based on a single PMOS sleep transistor and a dual threshold voltage CMOS technology is proposed in this paper for simultaneously reducing subthreshold and...
Zhiyu Liu, Volkan Kursun
ISVLSI
2002
IEEE
174views VLSI» more  ISVLSI 2002»
15 years 4 months ago
Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits
With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits ha...
Alice Wang, Anantha Chandrakasan, Stephen V. Koson...
105
Voted
DT
2006
109views more  DT 2006»
14 years 11 months ago
Test Consideration for Nanometer-Scale CMOS Circuits
The ITRS (International Technology Roadmap for Semiconductors) predicts aggressive scaling down of device size, transistor threshold voltage and oxide thickness to meet growing de...
Kaushik Roy, T. M. Mak, Kwang-Ting (Tim) Cheng
DAC
1999
ACM
15 years 4 months ago
Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS
The state dependence of leakage can be exploited to obtain modest leakage savings in CMOS circuits. However, one can modify circuits considering state dependence and achieve large...
Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy
VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
15 years 5 months ago
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology
As the IC process technology scales, the oxide thickness and operating voltage continues to decrease. The gate oxide thickness in recent and future IC process technology has appro...
Sanjeev K. Jain, Pankaj Agarwal