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» Low threshold CMOS circuits with low standby current
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ICCD
2000
IEEE
137views Hardware» more  ICCD 2000»
15 years 4 months ago
Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family
In this paper; we present a noise-immune highperformance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits, in comparison with Do...
Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh...
ENGL
2007
118views more  ENGL 2007»
14 years 11 months ago
Design of Low Power CMOS Crystal Oscillator with Tuning Capacitors
—A low power CMOS crystal oscillator was proposed with high accuracy by tuning capacitors. Based on the analysis concerning power consumption, start-up time, and frequency stabil...
Shun Yao, Hengfang Zhu, Xiaobo Wu
ARVLSI
2001
IEEE
305views VLSI» more  ARVLSI 2001»
15 years 3 months ago
Logic Design Considerations for 0.5-Volt CMOS
As the operating supply voltage for commercial CMOS devices falls below 2 V, research activities are underway to develop CMOS integrated circuits that can operate at supply voltag...
K. Joseph Hass, Jack Venbrux, Prakash Bhatia
ISCAS
2006
IEEE
119views Hardware» more  ISCAS 2006»
15 years 5 months ago
Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis
In this paper we present two polynomial time-complexity heuristic algorithms for optimization of gate-oxide leakage (tunneling current) during behavioral synthesis through simulta...
Saraju P. Mohanty, Elias Kougianos, Ramakrishna Ve...
ASPDAC
2006
ACM
135views Hardware» more  ASPDAC 2006»
15 years 5 months ago
Robust analytical gate delay modeling for low voltage circuits
— Sakurai-Newton (SN) delay metric [1] is a widely used closed form delay metric for CMOS gates because of simplicity and reasonable accuracy. Nevertheless it can be shown that t...
Anand Ramalingam, Sreekumar V. Kodakara, Anirudh D...