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FPGA
2001
ACM
145views FPGA» more  FPGA 2001»
15 years 9 months ago
Simultaneous logic decomposition with technology mapping in FPGA designs
Conventional technology mapping algorithms for SRAM-based Field Programmable Gate Arrays (FPGAs) are normally carried out on a fixed logic decomposition of a circuit. The impact o...
Gang Chen, Jason Cong
ICCCN
1997
IEEE
15 years 9 months ago
Time dependent priority scheduling for guaranteed QoS systems
With the advances in server technology, and the advent of fast Gigabit networks, it has become possible to support multi-media applications. To support the requirements for the tr...
Shailender Chaudhry, Alok N. Choudhary
ICMCS
1997
IEEE
142views Multimedia» more  ICMCS 1997»
15 years 9 months ago
A Rate Allocation Policy with MCR/PCR Support and Distributed ABR Implementation Using Explicit Rate Feedback
An important concept in the available bit rate (ABR) service model as defined by the ATM Forum is the minimum cell rate (MCR) guarantee as well as the peak cell rate (PCR) constra...
Yiwei Thomas Hou, Henry H.-Y. Tzeng, Shivendra S. ...
GECCO
2007
Springer
182views Optimization» more  GECCO 2007»
15 years 8 months ago
Stochastic training of a biologically plausible spino-neuromuscular system model
A primary goal of evolutionary robotics is to create systems that are as robust and adaptive as the human body. Moving toward this goal often involves training control systems tha...
Stanley Phillips Gotshall, Terence Soule
ICANNGA
2009
Springer
163views Algorithms» more  ICANNGA 2009»
15 years 8 months ago
Elitistic Evolution: An Efficient Heuristic for Global Optimization
A new evolutionary algorithm, Elitistic Evolution (termed EEv), is proposed in this paper. EEv is an evolutionary method for numerical optimization with adaptive behavior. EEv uses...
Francisco Viveros Jiménez, Efrén Mez...