102 search results - page 3 / 21 » Low-Transition Test Pattern Generation for BIST-Based Applic... |
77
Voted
VLSID
2002
IEEE
15 years 9 months ago
2002
IEEE
We describe a built-in test pattern generation method for scan circuits. The method is based on partitioning and storage of test sets. Under this method, a precomputed test set is...
70
Voted
ISCAS
1999
IEEE
15 years 1 months ago
1999
IEEE
The main objectives of Built-In Self Test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test ...
123
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EVOW
1999
Springer
15 years 1 months ago
1999
Springer
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
82
Voted
ICCAD
1997
IEEE
15 years 1 months ago
1997
IEEE
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...
XPU
2004
Springer
15 years 2 months ago
2004
Springer
Abstract. While there are many excellent acceptance testing tools and frameworks available today, this paper presents an alternative approach, involving generating code from tests ...