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» Low-power circuits using dynamic threshold devices
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DT
2006
109views more  DT 2006»
14 years 9 months ago
Test Consideration for Nanometer-Scale CMOS Circuits
The ITRS (International Technology Roadmap for Semiconductors) predicts aggressive scaling down of device size, transistor threshold voltage and oxide thickness to meet growing de...
Kaushik Roy, T. M. Mak, Kwang-Ting (Tim) Cheng
DAC
2005
ACM
15 years 10 months ago
System-level energy-efficient dynamic task scheduling
Dynamic voltage scaling (DVS) is a well-known low power design technique that reduces the processor energy by slowing down the DVS processor and stretching the task execution time...
Jianli Zhuo, Chaitali Chakrabarti
JCSC
2002
129views more  JCSC 2002»
14 years 9 months ago
Leakage Current Reduction in VLSI Systems
There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits re...
David Blaauw, Steven M. Martin, Trevor N. Mudge, K...
ICCAD
2006
IEEE
119views Hardware» more  ICCAD 2006»
15 years 3 months ago
Dynamic power management using machine learning
Dynamic power management (DPM) work proposed to date places inactive components into low power states using a single DPM policy. In contrast, we instead dynamically select among a...
Gaurav Dhiman, Tajana Simunic Rosing
ISLPED
2003
ACM
142views Hardware» more  ISLPED 2003»
15 years 2 months ago
Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization
We describe an optimization strategy for minimizing total power consumption using dual threshold voltage (Vth) technology. Significant power savings are possible by simultaneous a...
David Nguyen, Abhijit Davare, Michael Orshansky, D...