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» Lower Bounds in Distributed Computing
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DAC
2006
ACM
16 years 5 months ago
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
Yu Hu, Yan Lin, Lei He, Tim Tuan
IFIP
2004
Springer
15 years 10 months ago
The Inherent Queuing Delay of Parallel Packet Switches
The parallel packet switch (PPS) extends the inverse multiplexing architecture, and is extensively used as the core of contemporary commercial switches. A key factor in the perfor...
Hagit Attiya, David Hay
SSDBM
2010
IEEE
117views Database» more  SSDBM 2010»
15 years 9 months ago
Finding Top-k Similar Pairs of Objects Annotated with Terms from an Ontology
With the growing focus on semantic searches and interpretations, an increasing number of standardized vocabularies and ontologies are being designed and used to describe data. We ...
Arnab Bhattacharya, Abhishek Bhowmick, Ambuj K. Si...
COCO
2006
Springer
93views Algorithms» more  COCO 2006»
15 years 8 months ago
Making Hard Problems Harder
We consider a general approach to the hoary problem of (im)proving circuit lower bounds. We define notions of hardness condensing and hardness extraction, in analogy to the corres...
Joshua Buresh-Oppenheim, Rahul Santhanam
TON
2008
124views more  TON 2008»
15 years 4 months ago
Designing packet buffers for router linecards
-- Internet routers and Ethernet switches contain packet buffers to hold packets during times of congestion. Packet buffers are at the heart of every packet switch and router, whic...
Sundar Iyer, Ramana Rao Kompella, Nick McKeown