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DFT
2003
IEEE
106views VLSI» more  DFT 2003»
15 years 3 months ago
Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits
Transient faults in VLSI circuits could lead to disastrous consequences. With technology scaling, circuits are becoming increasingly vulnerable to transient faults. This papers pr...
Atul Maheshwari, Israel Koren, Wayne Burleson
ITC
1999
IEEE
78views Hardware» more  ITC 1999»
15 years 2 months ago
Minimized power consumption for scan-based BIST
Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture a...
Stefan Gerstendörfer, Hans-Joachim Wunderlich
ICCAD
1996
IEEE
102views Hardware» more  ICCAD 1996»
15 years 2 months ago
Bit-flipping BIST
A scan-based BIST scheme is presented which guarantees complete fault coverage with very low hardware overhead. A probabilistic analysis shows that the output of an LFSR which fee...
Hans-Joachim Wunderlich, Gundolf Kiefer
AINA
2004
IEEE
15 years 1 months ago
RED with Optimized Dynamic Threshold Deployment on Shared Buffer
Prior survey of RED algorithm deployment on multiqueue system with shared buffer was unfair and sensitive to congestion level by statically setting the parameters. In this paper, ...
Chengchen Hu, Bin Liu
EPEW
2006
Springer
15 years 1 months ago
Experimental Analysis of the Correlation of HTTP GET Invocations
In this paper we experimentally investigate if optimal retry times can be determined based on models that assume independence of successive tries. We do this using data obtained fo...
Philipp Reinecke, Aad P. A. van Moorsel, Katinka W...