Sciweavers

308 search results - page 38 / 62
» MCGREP - A Predictable Architecture for Embedded Real-Time S...
Sort
View
RTCSA
2009
IEEE
15 years 4 months ago
Branch Target Buffers: WCET Analysis Framework and Timing Predictability
—One step in the verification of hard real-time systems is to determine upper bounds on the worst-case execution times (WCET) of tasks. To obtain tight bounds, a WCET analysis h...
Daniel Grund, Jan Reineke, Gernot Gebhard
RTCSA
2009
IEEE
15 years 4 months ago
Towards Hardware Support for Common Sensor Processing Tasks
—Sensor processing is a common task within many embedded system domains, such as in control systems, the sensor feedback is used for actuator control. In this paper we have surve...
Adwait Gupte, Phillip Jones
ICAS
2008
IEEE
200views Robotics» more  ICAS 2008»
15 years 4 months ago
Connectivity of Thetis, a Distributed Hybrid Simulator, with a Mixed Control Architecture
—The purpose of this paper is to present the linkage of Thetis (a real time multi-vehicles hybrid simulator for heterogeneous vehicles) with a control architecture for the manage...
Olivier Parodi, Abdellah El Jalaoui, David Andreu
RTAS
2005
IEEE
15 years 3 months ago
Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
Harini Ramaprasad, Frank Mueller
93
Voted
CASES
2005
ACM
14 years 11 months ago
Architectural support for real-time task scheduling in SMT processors
In Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architec...
Francisco J. Cazorla, Peter M. W. Knijnenburg, Riz...