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CJ
2010
80views more  CJ 2010»
14 years 9 months ago
Verifying a Synthesized Implementation of IEEE-754 Floating-Point Exponential Function using HOL
rder logic (HOL) theorem prover. The high ability of abstraction in the HOL verification system allows its use for the verification task over the whole design path of the circuit, ...
Behzad Akbarpour, Amr T. Abdel-Hamid, Sofiè...
DATE
2006
IEEE
96views Hardware» more  DATE 2006»
15 years 3 months ago
A methodology for FPGA to structured-ASIC synthesis and verification
Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden a...
Michael Hutton, Richard Yuan, Jay Schleicher, Greg...
EUROSYS
2007
ACM
15 years 6 months ago
Removing the memory limitations of sensor networks with flash-based virtual memory
Virtual memory has been successfully used in different domains to extend the amount of memory available to applications. We have adapted this mechanism to sensor networks, where,...
Andreas Lachenmann, Pedro José Marró...