1342 search results - page 20 / 269 » MEMS Design And Verification |
79
Voted
TACAS
2010
Springer
14 years 7 months ago
2010
Springer
Abstract. Intermediate languages are a paradigm to separate concerns in software verification systems when bridging the gap between programming languages and the logics understood ...
DAC
2005
ACM
15 years 10 months ago
2005
ACM
We describe IODINE, a tool to automatically extract likely design properties using dynamic analysis. A practical bottleneck in the formal verification of hardware designs is the n...
75
Voted
DAC
2003
ACM
15 years 10 months ago
2003
ACM
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or...
EH
2005
IEEE
15 years 3 months ago
2005
IEEE
The Evolvable Computation Group, at NASA’s Jet Propulsion Laboratory, is tasked with demonstrating the utility of computational engineering and computer optimized design for com...
68
Voted
DAC
1994
ACM
15 years 1 months ago
1994
ACM
Functional and timing verification are currently the bottlenecks in many design efforts. Simulation and emulation are extensively used for verification. Formal verification is now...