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DSD
2003
IEEE
123views Hardware» more  DSD 2003»
15 years 3 months ago
Design Tools and Reusable Libraries for FPGA-Based Digital Circuits
This paper suggests tools that provide significant improvements in the design and verification of FPGAbased digital circuits. These tools include reusable specifications of hardwa...
Valery Sklyarov, Iouliia Skliarova, Pedro Almeida,...
SIGSOFT
2003
ACM
15 years 10 months ago
Towards scalable compositional analysis by refactoring design models
Automated finite-state verification techniques have matured considerably in the past several years, but state-space explosion remains an obstacle to their use. Theoretical lower b...
Yung-Pin Cheng, Michal Young, Che-Ling Huang, Chia...
ISQED
2003
IEEE
113views Hardware» more  ISQED 2003»
15 years 3 months ago
Using Integer Equations for High Level Formal Verification Property Checking
This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verificatio...
Bijan Alizadeh, Mohammad Reza Kakoee
FMCAD
2007
Springer
15 years 1 months ago
Boosting Verification by Automatic Tuning of Decision Procedures
Parameterized heuristics abound in computer aided design and verification, and manual tuning of the respective parameters is difficult and time-consuming. Very recent results from ...
Frank Hutter, Domagoj Babic, Holger H. Hoos, Alan ...
ACL2
2006
ACM
15 years 1 months ago
Combining ACL2 and an automated verification tool to verify a multiplier
We have extended the ACL2 theorem prover to automatically prove properties of VHDL circuits with IBM's Internal SixthSense verification system. We have used this extension to...
Erik Reeber, Jun Sawada