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» MEMS Design And Verification
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ASPDAC
2006
ACM
109views Hardware» more  ASPDAC 2006»
15 years 3 months ago
Cycle error correction in asynchronous clock modeling for cycle-based simulation
— As the complexity of SoCs is increasing, hardware/software co-verification becomes an important part of system verification. C-level cycle-based simulation could be an efficien...
Junghee Lee, Joonhwan Yi
ACSD
2001
IEEE
74views Hardware» more  ACSD 2001»
15 years 1 months ago
From Code to Models
One of the corner stones of formal methods is the notion traction enables analysis. By the construction of act model we can trade implementation detail for analytical power. The i...
Gerard J. Holzmann
FORMATS
2007
Springer
15 years 1 months ago
Combining Formal Verification with Observed System Execution Behavior to Tune System Parameters
Resource limited DRE (Distributed Real-time Embedded) systems can benefit greatly from dynamic adaptation of system parameters. We propose a novel approach that employs iterative t...
Minyoung Kim, Mark-Oliver Stehr, Carolyn L. Talcot...
MICRO
2008
IEEE
137views Hardware» more  MICRO 2008»
14 years 9 months ago
Verification of chip multiprocessor memory systems using a relaxed scoreboard
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to ...
Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin...
ICCAD
2003
IEEE
115views Hardware» more  ICCAD 2003»
15 years 6 months ago
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits
This paper presents an efficient method for verifying hazard freedom in timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that utilize explicit tim...
Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda