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PADL
2007
Springer
15 years 10 months ago
From Zinc to Design Model
We describe a preliminary implementation of the high-level modelling language Zinc. This language supports a modelling methodology in which the same Zinc model can be automatically...
Reza Rafeh, Maria J. García de la Banda, Ki...
SAMOS
2007
Springer
15 years 10 months ago
A Model-Driven Automatically-Retargetable Debug Tool for Embedded Systems
Abstract. Contemporary SoC designs ask for system-level debugging tools suitable to heterogeneous platforms. Such tools will have to rely on some low-level model-driven debugging e...
Max R. de O. Schultz, Alexandre K. I. Mendon&ccedi...
GLVLSI
2006
IEEE
95views VLSI» more  GLVLSI 2006»
15 years 10 months ago
Test generation using SAT-based bounded model checking for validation of pipelined processors
Functional verification is one of the major bottlenecks in microprocessor design. Simulation-based techniques are the most widely used form of processor verification. Efficient ...
Heon-Mo Koo, Prabhat Mishra
DATE
2005
IEEE
110views Hardware» more  DATE 2005»
15 years 10 months ago
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
The increasing complexity and the short life cycles of embedded systems are pushing the current system-onchip designs towards a rapid increasing on the number of programmable proc...
Alexandre M. Amory, Marcelo Lubaszewski, Fernando ...
ICMB
2005
IEEE
98views Business» more  ICMB 2005»
15 years 10 months ago
Security Issues in SIP Signaling in Wireless Networks and Services
SIP appears to be a powerful and useful signaling protocol supporting mobility for wireless IP networks but it has inherent weaknesses and dangers. This paper is a study on the se...
Elthea T. Lakay, Johnson I. Agbinya