Sciweavers

877 search results - page 174 / 176
» MXQuery with Hardware Acceleration
Sort
View
FPL
2008
Springer
153views Hardware» more  FPL 2008»
13 years 7 months ago
Exploring FPGA network on chip implementations across various application and network loads
Abstract-The network on chip will become a future general purpose interconnect for FPGAs much like today's standard OPB or PLB bus architectures. However, performance characte...
Graham Schelle, Dirk Grunwald
ERSA
2006
129views Hardware» more  ERSA 2006»
13 years 7 months ago
Group-Alignment based Accurate Floating-Point Summation on FPGAs
Floating-point summation is one of the most important operations in scientific/numerical computing applications and also a basic subroutine (SUM) in BLAS (Basic Linear Algebra Sub...
Chuan He, Guan Qin, Mi Lu, Wei Zhao
BMCBI
2010
218views more  BMCBI 2010»
13 years 6 months ago
Fast multi-core based multimodal registration of 2D cross-sections and 3D datasets
Background: Solving bioinformatics tasks often requires extensive computational power. Recent trends in processor architecture combine multiple cores into a single chip to improve...
Michael Scharfe, Rainer Pielot, Falk Schreiber
CLUSTER
2007
IEEE
13 years 10 months ago
Efficient asynchronous memory copy operations on multi-core systems and I/OAT
Bulk memory copies incur large overheads such as CPU stalling (i.e., no overlap of computation with memory copy operation), small register-size data movement, cache pollution, etc...
Karthikeyan Vaidyanathan, Lei Chai, Wei Huang, Dha...
AVI
2008
13 years 8 months ago
Agent warp engine: formula based shape warping for networked applications
Computer visualization and networking have advanced dramatically over the last few years, partially driven by the exploding video game market. 3D hardware acceleration has reached...
Alexander Repenning, Andri Ioannidou