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FPL
2011
Springer
203views Hardware» more  FPL 2011»
14 years 1 months ago
Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms
Abstract—In the clinical applications, medical image registrations on the images taken from different times and/or through different modalities are needed in order to have an obj...
Jason Cong, Muhuan Huang, Yi Zou
102
Voted
ICCD
2008
IEEE
159views Hardware» more  ICCD 2008»
15 years 10 months ago
Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor
— Heterogeneous Chip Multiprocessors (HMPs), such as the Cell Broadband Engine, offer a new design optimization opportunity by allowing designers to provide accelerators for appl...
Michael Gschwind
124
Voted
ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
15 years 7 months ago
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
Nathan Clark, Jason A. Blome, Michael L. Chu, Scot...
130
Voted
TVLSI
2010
14 years 8 months ago
Bandwidth Adaptive Hardware Architecture of K-Means Clustering for Video Analysis
K-Means is a clustering algorithm that is widely applied in many fields, including pattern classification and multimedia analysis. Due to real-time requirements and computational-c...
Tse-Wei Chen, Shao-Yi Chien
ISQED
2010
IEEE
194views Hardware» more  ISQED 2010»
15 years 8 months ago
Accelerating trace computation in post-silicon debug
— Post-silicon debug comprises a significant and highly variable fraction of the total development time for large chip designs. To accelerate post-silicon debug, BackSpace [1, 2...
Johnny J. W. Kuan, Steven J. E. Wilton, Tor M. Aam...