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DATE
2010
IEEE
135views Hardware» more  DATE 2010»
15 years 7 months ago
Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits
— To overcome issues originating from the CMOS technology, a large-scale reconfigurable data-path (LSRDP) processor based on single-flux quantum circuits is introduced. LSRDP is ...
Farhad Mehdipour, Hiroaki Honda, Hiroshi Kataoka, ...
113
Voted
FPL
2009
Springer
101views Hardware» more  FPL 2009»
15 years 6 months ago
An accelerator for K-TH nearest neighbor thinning based on the IMORC infrastructure
The creation and optimization of FPGA accelerators comprising several compute cores and memories are challenging tasks in high performance reconfigurable computing. In this paper...
Tobias Schumacher, Christian Plessl, Marco Platzne...
127
Voted
ERSA
2009
131views Hardware» more  ERSA 2009»
14 years 11 months ago
Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays
An effective way to implement image processing applications is to use embedded processors with dynamically reconfigurable accelerator cores. The processing speed of these processor...
Hasitha Muthumala Waidyasooriya, Masanori Hariyama...
ISCA
1998
IEEE
145views Hardware» more  ISCA 1998»
15 years 6 months ago
Multi-Level Texture Caching for 3D Graphics Hardware
Traditional graphics hardware architectures implement what we call the push architecture for texture mapping. Local memory is dedicated to the accelerator for fast local retrieval...
Michael Cox, Narendra Bhandri, Michael Shantz
DATE
2008
IEEE
156views Hardware» more  DATE 2008»
15 years 8 months ago
Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications
Embedded systems are becoming increasingly complex. Besides the additional processing capabilities, they are characterized by high diversity of computational models coexisting in ...
Antonio Carlos Schneider Beck, Mateus B. Rutzig, G...