877 search results - page 41 / 176 » MXQuery with Hardware Acceleration |
FPL
2003
Springer
15 years 7 months ago
2003
Springer
This paper describes the implementation of the L3 maze routing accelerator in an FPGA. L3 supports fast single-layer and multi-layer routing, preferential routing, and rip-up-and-r...
ISCAS
2006
IEEE
15 years 8 months ago
2006
IEEE
In this paper, we propose a cost-effective reconfigurable accelerator for the platform-based system-on-a-chip (SoC) design. Based on the proposed design methodology, the reconfigu...
ISCA
1999
IEEE
15 years 6 months ago
1999
IEEE
Future computing workloads will emphasize an architecture's ability to perform relatively simple calculations on massive quantities of mixed-width data. This paper describes ...
141
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VTC
2010
IEEE
15 years 8 days ago
2010
IEEE
—In this paper we present an architectural analysis of a smart DMA (sDMA) controller for protocol stack acceleration in mobile devices supporting 3GPP’s Long Term Evolution (LT...
104
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FPL
2010
Springer
14 years 12 months ago
2010
Springer
FPGA devices are mostly utilized for customized application designs with heavily pipelined and aggressively parallel computations. However, little focus is normally given to the FP...